Speakers—Gelato ICE | Singapore | October 2007
Yurong Chen, Intel
Yurong Chen is a researcher at the Intel Microprocessor Technology Lab, Beijing (Intel China Research Center). Currently he conducts research on parallel processing of emerging applications, scalable workloads, and benchmarking and performance analysis for next-generation microprocessors/platforms. He joined Intel in 2004. Before that he did two years postdoctoral research on large-scale scientific computing in the Institute of Software, Chinese Academy of Sciences. He received his Ph.D. degree from Tsinghua University in 2002. His e-mail is yurong.chen at intel.com.
The Parallel Framework for Realizing the Power of Multi-Core Processors
Steven Ericsson-Zenith, Institute for Advanced Science & Engineering
Steven Ericsson-Zenith is a Scholar at the Institute for Advanced Science & Engineering. He obtained his doctorate in Computer Science from the University of Pierre and Marie Curie in Paris in 1992. His dissertation discusses his work at INMOS on the Transputer microprocessor and the parallel programming language Occam as a part of David May's Computer Architecture team and his subsequent work at Yale University with David Gelernter's Linda Group.
He first introduced the Process Oriented Programming model in his work at Yale University. This model consists of parallel programming data types that allow programmers to express distributed data structures and the processes that act upon them. The model addresses well known problems in the general purpose programming of parallel computers, provides ease of programming with powerful logically shared data structures while maintaining the underlying rigor of a CSP formal basis.
The Process Orient Programming model is being implemented for many-core processors in the language Carnap (http://carnap.info).
General Purpose Programming of Many-Core Devices and Many-Core Systems
Colt Gan, Intel
Colt Gan joined Intel in 1995. Worked as senior software engineer, senior consultant and lead instructor in various Intel teams. Mainly focused on new technology enabling for China market. Colt now leads a technical consultant engineer team to support Intel software tools in APAC.
Intel Threading Building Block (TBB)
James Gan, IBM
Zhi Gan, a software engineer at IBM China Emerging Technology Institute. He joined IBM in 2005 after receiving a Ph.D degree in computer security from Shanghai JiaoTong University. Mr. Gan has extensive experience in SOA, Parallel Programming Models, and Eclipse. His current focus is parallel programming models for multi-core, model-driven development with patterns, and next generation tooling. Zhi can be contacted at ganzhi@cn.ibm.com
Model-Driven Development Tool for Parallel Applications
Wei Chung Hsu, University of Minnesota
Wei Chung Hsu received a PhD in Computer Science from the University of Wisconsin, Madison, in 1987. Currently, he is a full professor in the Department of Computer Science and Engineering at the University of Minnesota. From 1997 to 1999, he was a Runtime Optimization Architect in the California Language Lab at HP. From 1993 to 1997, he was a Technical Lead in the compiler team responsible for developing and releasing an optimizing compiler for the HP PA-8000 systems. Prior to joining HP, he was a Senior Software Engineer and an Architect at Cray Research, in Chippewa Falls, Wisconsin. His current research interests include high-performance computing systems and architectures, in particular, runtime optimization systems, optimizing compilers, and cache-related optimization techniques.
Dynamic Optimization - An Open Discussion
Dynamic Helper Thread Generation
Wen-mei W. Hwu, University of Illinois at Urbana-Champaign
Wen-mei W. Hwu holds the Sanders-AMD Endowed Chair in the Department of Electrical and Computer Engineering, University of Illinois at Urbana-Champaign. His research interests are in the areas of architecture, implementation, and software for high-performance computer systems. He is the director of the IMPACT research group (www.crhc.uiuc.edu/Impact). For his contributions in research and teaching, he received the Eta Kappa Nu Holmes MacDonald Outstanding Teaching Award, the ACM SigArch Maurice Wilkes Award, the ACM Grace Murray Hopper Award, the Tau Beta Pi Daniel C. Drucker Eminent Faculty Award, and the ISCA Most Influential Paper Award. He is a fellow of IEEE and ACM. Hwu serves on the Executive Committee of the MARCO/DARPA C2S2 (www.c2s2.org) and GSRC (www.gigascale.org) Focus Research Centers. He leads the GSRC Concurrent Systems Theme with Kurt Keutzer. He also serves on the Gelato Steering Committee. Dr. Hwu received his PhD degree in Computer Science from the University of California, Berkeley.
GPU Computing Research at UIUC
Sverre Jarp, European Organization for Nuclear Research
Sverre Jarp is the Chief Technology Officer at the CERN openlab, a joint collaboration with leading industrial partners in order to assess cutting-edge information technology for the Large Hadron Collider’s Computing Grid from 2007 onwards.
He has been working in computing at CERN for over 30 years and has held various managerial and technical positions, promoting advanced but cost-effective computing solutions for the Laboratory. In 2001-2002, he spent a sabbatical year at HP Labs (Palo Alto, USA). Inside openlab, his main focus is currently compilers and platform optimization as well as virtualization and grid middleware.
S. Jarp holds a degree in Theoretical Physics from the Norwegian University of Science and Technology in Trondheim.
Parallel Processing Models and Research at CERN
David Kirk, Nvidia
David Kirk has been NVIDIA's Chief Scientist since January 1997. His contribution includes leading NVIDIA graphics technology development for today’s most popular consumer entertainment platforms. In 2006, Dr. Kirk was elected to the National Academy of Engineering (NAE) for his role in bringing high-performance graphics to personal computers. Election to the NAE is among the highest professional distinctions awarded in engineering. In 2002, Dr. Kirk received the SIGGRAPH Computer Graphics Achievement Award for his role in bringing high-performance computer graphics systems to the mass market. From 1993 to 1996, Dr. Kirk was Chief Scientist, Head of Technology for Crystal Dynamics, a video game manufacturing company. From 1989 to 1991, Dr. Kirk was an engineer for the Apollo Systems Division of Hewlett-Packard Company. Dr. Kirk is the inventor of 50 patents and patent applications relating to graphics design and has published more than 50 articles on graphics technology. Dr. Kirk holds B.S. and M.S. degrees in Mechanical Engineering from the Massachusetts Institute of Technology and M.S. and Ph.D. degrees in Computer Science from the California Institute of Technology.
Massively Parallel GPU Computing with NVIDIA's CUDA
Xiao-Feng Li, Intel
Xiao-Feng is a VM architect in the System Software Division of the Intel Software and Solutions Group, where he leads a team developing managed runtime technologies. Prior to his current position, Xiao-Feng was a research manager in the Micro-processor Technology Labs of the Intel Corporate Technology Group. Before he joined Intel, Xiao-Feng worked at the Nokia Reseach Center on mobile and network technologies. Xiao-Feng is active in the open source community, frequently training and giving lectures. Xiao-Feng's current interests are in programming language design and implementations, focusing on runtime technologies and their interactions with underlying platforms.
Shin-Ming Liu, HP
Shin-Ming Liu is the Section Manager for the Optimization Technology Section of the Java, Compiler, and Tools Lab at HP in Cupertino, California. Liu led the development team for all levels of optimization in Java and compilers targeted for the Itanium processor. He has led the reinvention of compiler development methodology by focusing on modulization, memory footprint control, canonical internal representation, and automatic error detection. Before joining HP, he worked at MIPS/SGI in the area of compiler front end, middle end, back end, and linker. He has co-authored several technical publications and holds several US patents in the field of compiler optimization.
HP Compiler Lab - The Many-Core Perspective
Judy Qiu, Indiana University
Qiu received a Masters degree in Computer Science and Engineering at Beihang University and a Masters and Ph.D in Computer and Information Science from Syracuse University. She is now a Postdoctoral researcher at the Bloomington campus of Indiana University. Her research interests include distributed and parallel computing, grid computing, collaboration systems, and computer graphics. She is involved in the SALSA many-core computing project which is developing a hybrid model of parallel computing that links grids, clusters and multi-core chips. SALSA is building a suite of parallel data mining algorithms for applications including Geographical Information Systems, cheminformatics, bioinformatics, and speech recognition. Her interests here include parallel algorithms, performance evaluation and programming models.
Christoph Schaefer, University of Karlsruhe
Christoph Schaefer received a Masters degree in Computer Science at the University of Karlsruhe, Germany. He is now an assistant researcher at the Institute of Programming Structures and Data Organization at the University of Karlsruhe. He is involved in the Multicore Software Engineering Research Group, which focuses on investigating software engineering concepts, methods, and tools for developing reliable, parallel software. Christoph’s research interests include parallel patterns, tunable architectures and auto-tuning.
Software Engineering for Multi-Core Systems - An Experience Report
Robert Schreiber, HP
Rob Schreiber is a Distinguished Technologist in and Assistant Director of the Exascale Computing Lab at Hewlett Packard Laboratories. Dr. Schreiber received a BA in mathematics from Cornell in 1972 and a PhD in Computer Science from Yale in 1977. He is known for research in sequential and parallel algorithms for matrix computation and compiler optimization for parallel languages. He was a professor of Computer Science at Stanford and at RPI and was chief scientist of the Saxpy Computer company. He was a co-developer of the sparse matrix extension of Matlab, and a leading designer of the High Performance Fortran programming language. He was one of the developers of the NAS parallel benchmarks. At HP, Rob helped lead the PICO Project, which developed a system for embedded processor synthesis from high-level specifications. In 2007 he was named as a Distinguished Scientist by the Association for Computing Machinery.
Lei Shang, Institute of Computing Technology, CAS
Lei Shang received a Masters in Computational Mathematics from Northwestern Polytechnical University. He is an assistant researcher at the Advanced Compiling Technology Lab in the Institute of Computing Technology, Chinese Academy of Sciences. His research interests include parallel algorithms, parallel languages and optimization techniques. He is now involved in a research group which focuses on parallel programming models for hyper parallel systems. Shang can be reached at shanglei@ict.ac.cn.
Communication Analysis and Optimized Mapping of Explicit Parallel Codes
Yao Shi, Tsinghua University
Yao Shi is a PhD candidate in the Department of Computer Science and Technology, Tsinghua University. He received a Bachelor degree from Tsinghua University in 2004. He is a member of the Open64 Compiler group and his current interest is concurrent program analysis. Shi can be reached at shiyao00@mails.tsinghua.edu.cn.
May Happen in Parallel Analysis
Mark K. Smith, Gelato Central Operations
Mark K. Smith is the Managing Director of the Gelato Federation. He works with Federation members and sponsors around the world, fostering collaborative relationships among members, sponsors, and the general community to advance the Linux-Itanium platform. Mark leads a technical team at the University of Illinois and dedicates time to educating the general community about the advantages of the platform. Prior to joining Gelato, he worked in the software industry for 10 years. Mark holds a PhD in Engineering from the University of Illinois.
Xinmin Tian, Intel
Xinmin Tian holds a PhD in Computer Science. He is a Principal Engineer and Compiler Architect at Intel. Xinmin leads parallelization, vectorization, compiler parallel debugging support and transactional memory research and development projects of Intel C++ and FORTRAN compilers for Intel IA-32, Intel 64, and Itanium multi-core architectures. He has over 30 refereed technical publications on compiler optimizations, parallel computing, and multi-threaded architectures. Xinmin Tian is a coauthor of "The Software Optimization Cookbook" (Second Edition) at Intel Press published in 2006, and a main contributor for the "Multi-Core Programming" book published by Intel Press in 2006. Xinmin Tian has 20 patents pending in the areas of compiler optimizations, parallelization, and multi-core architectures. He also served on program committees for research conferences and has been a referee for technical journals and conferences.
Taking Multi-Core and Parallelism Seriously: The Intel Perspective
Li Zhang, University of Amsterdam
Li Zhang received a Masters degree in Computer Engineering at Delft University of Technology, the Netherlands. Currently, he is a PhD candidate and assistant researcher in the Informatics Institute at the University of Amsterdam. His research interests include computer architecture and implementation, memory architecture, and programming model. He is involved in the Microgrid project at computer system architecture group, which focuses on multi-core programming model, its computer architecture and memory architecture.
Scalable Concurrency in Many-Core Processors